Widely used is a COF (CHIP ON FLEXIBLE PRINTED CIRCUIT) semiconductor device mountable in a narrow space or a space of complex shape. In the COF semiconductor device, a semiconductor element is bonded to or mounted on (connected to) a flexible wiring board. In the flexible wiring board, wiring patterns are formed on a flexible insulating tape substrate, referred as a tape carrier. A conventional COF semiconductor device is disclosed, for example, in Japanese Unexamined Patent Publication No. 27246/1989 (Tokukaisho 64-27246, disclosure date: Jan. 30, 1989).
FIGS. 7 to 9 illustrate a bonding structure for bonding the flexible wiring board with the semiconductor element in the conventional COF semiconductor device. FIG. 7 schematically shows a plan view of a flexible wiring board 101 in the conventional COF semiconductor device. FIG. 8 schematically shows a plan view of an area in which the semiconductor element is mounted on the flexible wiring board 101 shown in FIG. 7. FIG. 9 schematically shows a cross-sectional view of the conventional COF semiconductor device 110. Note that, FIG. 8 shows a semiconductor element 111 by the dashed line, and its bump electrodes 112 (semiconductor connection terminals) by the chain double-dashed line.
As shown in FIG. 7, in the conventional flexible wiring board 101, a plurality of the wiring patterns 103 are formed on the insulating tape substrate 102. As shown FIGS. 7 and 8, one ends of the wiring patterns are connected to the corresponding bump electrodes 112 of the semiconductor element 111. The above one ends are referred to as inner leads 131. As shown FIG. 7, the other ends of the wiring patterns 103 are connected to corresponding outer circuits. The above other ends are referred to as outer leads 132.
Further, a surface of the flexible wiring board 101 may be covered with an insulating solder resist 141. The solder resist 141 protects the wiring patterns 103.
However, in a semiconductor 111 mounting area, which is the area that is surrounded by the dashed line, the outer lead 132 and its peripheral part are not covered by the solder resist 141 and exposed. Hereinafter, a covered area with the solder resist 141 is referred to as a solder resist covering part, and an uncovered area with the solder resist 141, in which the inner lead 131 are provided, is referred to as a solder resist opening. As shown in FIG. 8, in the conventional flexible wiring board 101, the solder resist opening 142 includes (exposes) whole of the semiconductor 111 mounting area, and thus, is wider than the area.
As shown in FIG. 9, in the conventional COF semiconductor device 110, the semiconductor element 111 is mounted on the flexible wiring board 101. On mounting, the electrodes 112 of the semiconductor element 111 and the corresponding inner leads 131 of the flexible wiring board 101 are bonded to each other. The bonding of the bump electrodes 112 to the corresponding inner leads 131 is generally carried out by applying heat and pressure thereby to alloy their materials with each other or to bond them by thermocompression. After bonding, insulating resin 114 may be injected between the flexible wiring board 101 and the semiconductor element 111, and then cured, in order to prevent the inner lead 131 from being exposed.
As described above, a solder resist opening 142 on a flexible wiring board 101 includes (exposes) whole of the semiconductor element 111 mounting area, and is wider than the area, in the above conventional flexible wiring board. Such a flexible wiring board 101 is so arranged that not only each inner lead 131 which is bonded to a corresponding electrode 112, but also the other portion of each wiring pattern 103 are within the solder resist opening 142, and exposed therethrough.
Thereby, on mounting the semiconductor element 111, contact between another portions than the bump electrodes 112 on the semiconductor element 111 and wiring patterns 103 can disadvantageously occur, hereby the semiconductor element 111 can be disadvantageously damaged. Such disadvantageous contact may occur, for example, when the semiconductor element 111 is in contact with that end portion 133 of the wiring pattern 103 which is on the same end as the inner lead 131 but is not included in the inner lead 131, or with a wiring 134 formed within the solder resist opening 142. Such disadvantageous contact may also occur, for example, when a wiring pattern 103 and an edge (end) of the semiconductor element 111 are in contact with each other.